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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA /2, /4, /8 Clock MC10EL34 MC100EL34 Generation Chip The MC10/100EL34 is a low skew /2, /4, /8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC coupled into the device (see Interfacing section of the ECLinPSTM Data Book DL140/D). If a single-ended input is to be used, the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the EL34 under single-ended input conditions, as a result, this pin can only source/sink up to 0.5mA of current. The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input. Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. 16 1 D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 PIN DESCRIPTION PIN CLK EN MR VBB Q0 Q1 Q2 FUNCTION Diff Clock Inputs Sync Enable Master Reset Reference Output Diff /2 Outputs Diff /4 Outputs Diff /8 Outputs FUNCTION TABLE * * * * * 50ps Output-to-Output Skew Synchronous Enable/Disable Master Reset for Synchronization 75k Internal Input Pulldown Resistors >1000V ESD Protection LOGIC DIAGRAM AND PINOUT ASSIGNMENT CLK VCC 16 EN 15 D Q /2 Q R NC 14 CLK 13 CLK 12 VBB 11 MR 10 VEE 9 EN L H X MR L L H FUNCTION Divide Hold Q0-3 Reset Q0-3 Z ZZ X R /4 Q R /8 Q R Z = Low-to-High Transition ZZ = High-to-Low Transition 1 Q0 2 Q0 3 VCC 4 Q1 5 Q1 6 VCC 7 Q2 8 Q2 12/93 (c) Motorola, Inc. 1996 3-1 REV 2 MC10EL34 MC100EL34 AC/DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = GND) -40C Symbol fMAX IEE VBB IIH tPLH tPHL tSKEW tS tH VPP VCMR tr tf Characteristic Max Toggle Frequency Power Supply Current 10EL 100EL -1.43 -1.38 150 960 900 750 100 400 250 250 -2.0 275 -0.4 525 400 250 250 -2.0 275 -0.4 525 1200 1140 1060 960 900 750 100 400 250 250 -2.0 275 -0.4 525 Min 1100 39 39 -1.30 -1.26 -1.38 -1.38 Typ Max Min 1100 39 39 -1.27 -1.26 150 1200 1140 1060 960 900 750 100 400 250 250 V -2.0 275 -0.4 525 ps -1.35 -1.38 0C Typ Max Min 1100 39 39 -1.25 -1.31 -1.26 -1.38 150 1200 1140 1060 970 910 790 100 25C Typ Max Min 1100 39 42 -1.19 -1.26 150 1210 1150 1090 85C Typ Max Unit MHz mA V ps Output Reference 10EL Voltage 100EL Input High Current Propagation CLKQ0 Delay to CLKQ1,2 Output MRQ Within-Device Skew Setup Time EN Hold Time EN Minimum Input Swing CLK Common Mode Range CLK Output Rise/Fall Times Q (20% - 80%) ps ps ps mV Internal Clock Disabled CLK Q0 Q1 Q2 EN Internal Clock Enabled The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their next states in the same manner, time and relationship as they would have had the EN signal not been asserted. Figure 1. Timing Diagram MOTOROLA 3-2 ECLinPS and ECLinPS Lite DL140 -- Rev 3 MC10EL34 MC100EL34 OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 ECLinPS and ECLinPS Lite DL140 -- Rev 3 3-3 *MC10EL34/D* MC10EL34/D MOTOROLA |
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